Verilog Styles for Synthesis of Digital Systems

For senior/graduate-level courses in Digital Hardware Design/Verilog. This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students-e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications.

The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester.